(1) Field of the Invention
The present invention relates to a solid-state imaging device.
(2) Description of the Related Art
A solid-state imaging device detects, as an electric signal, electric charge that is obtained through photoelectrical conversion and accumulated in a photodiode. In particular, it is made up of cells and signal detection circuits which are arranged in a two-dimensional array (vertically and horizontally) on a semiconductor substrate.
Conventionally, solid-state imaging devices such as a charge-coupled device (CCD) image sensor and a metal-oxide semiconductor (MOS) image sensor are well known. In a MOS-type image sensor, signal charge generated through conversion by a photoelectrical conversion region (photodiode) is amplified by a transistor. The main features of such MOS-type image sensor are not only its high sensitivity and low power consumption but also its capability of single power operation. To be more specific, a potential in a signal charge accumulation region is modulated by signal charge generated through photoelectric conversion, and an amplification coefficient of an amplifying transistor varies depending on the potential. Since a MOS-type image sensor includes an amplifying transistor in each pixel, reduction in the pixel size and increase in the number of pixels are expected.
A MOS-type image sensor has an advantage that it is easy to integrate various circuits, such as peripheral circuits (a resistor circuit and a timing circuit), an analog-to-digital (A/D) conversion circuit, an instruction circuit, a digital-to-analog (D/A) conversion circuit and a digital signal processor (DSP), on the same substrate. Such integration of functional circuits and MOS-type image sensor on the same chip achieves cost reduction.
FIG. 1 shows one example of a schematic circuit diagram of a MOS-type image sensor. An image capture area 10 is made up of a plurality of cells (11-1-1, 11-1-2, . . . 11-3-3) which are arranged in a tow-dimensional array.
Each cell 11 is made up of a photodiode 12 (12-1-1, 12-1-2, . . . 12-3-3) that is a photoelectrical conversion element, an electric charge transfer transistor 13 (13-1-1, 13-1-2, . . . 13-3-3), a reset transistor 14 (14-1-1, 14-1-2, . . . 14-3-3) for removing electric charge, and an amplifying transistor 15 (15-1-1, 15-1-2, . . . 15-3-3). In such cell, a photoelectrical conversion region is made up of the photodiode 12 and the electric charge transfer transistor 13, and a signal detection circuit region is made up of the reset transistor 14 and the amplifying transistor 15.
In the area around the image capture area 10, peripheral circuits such as a horizontal shift register 21 and a vertical shift register 22 are arranged. A horizontal pixel selection line 24 and a reset line 23 each select the cell positions in the horizontal direction using the horizontal shift register 21. The horizontal pixel selection line 24 is connected to the gate of each electric charge transfer transistor 13 in order to determine the line for reading out signal charge. A vertical voltage input transistor 28 is connected to a vertical signal line 26 in order to select the cell positions in the vertical direction.
Next, FIG. 2 and FIGS. 3A and 3B show the top view and the cross-sectional views of a MOS-type solid-state imaging device that is one example of a conventional solid-state imaging device.
FIG. 2 shows the top view of such MOS-type solid-state imaging device. The top surface is made up of the following three regions: an electric charge transfer transistor including a photodiode 101, a transfer gate 103 and a detection capacitor 104; a reset transistor including the detection capacitor 104, a reset gate electrode 108 and a drain region 106; and an amplifying transistor 105 including the drain region 106, a source region 115 and an amplifying gate 114.
FIGS. 3A and 3B show the cross-sectional views of the MOS-type solid-state imaging device. FIG. 3A shows the cross section A-A′ in FIG. 2. On a semiconductor substrate 113, there are a phototransistor region, a reset transistor region and the electric charge amplifying transistor 105. The phototransistor region includes: the photodiode 101; the transfer gate 103 which is made up of a transfer gate electrode of a transfer transistor for transferring the electric charge generated from incident light and accumulated in the photodiode 101 and a gate insulating layer 107; and the detection capacitor 104 for accumulating the electric charge transferred from the photodiode 101 via the transfer gate 103. The reset transistor region includes, as a source region, the gate electrode 108, the drain region 106 and the above detection capacitor 104. The electric charge amplifying transistor 105 includes the drain region 106, the gate electrode 114 and the source region 115. The gate insulating layer is made of silicon oxides (SiO2) or silicon nitride (SiN). FIG. 3B shows the cross section B-B′ in FIG. 2. The channel width W below the gate is determined by the width of the area between the element isolation regions 110.
The operating principle of such MOS-type solid-state imaging device is as follows. The light detected by the photodiode 101 is converted into electric charge, and the electric charge is transferred to the detection capacitor 104 by turning on the transfer gate 103. Then, the electric charge accumulated in the detection capacitor 104 is transferred to the electric charge amplifying transistor 105 for performing signal amplification processing. Here, the reset gate electrode 108 is formed in order to completely remove the electric charge accumulated in the detection capacitor 104 therefrom, before the electric charge accumulated in the photodiode 101 is transferred to the detection capacitor 104 by turning on the transfer gate 103. By turning on the reset gate electrode 108 before transferring the electric charge to the detection capacitor 104, it becomes possible to completely transfer the charge to the drain region 106. In addition, the drain region 106 needs to be applied a plus voltage so that it has the higher voltage than the detection capacitor 104. This makes it possible to completely remove the carriers in the detection capacitor 104.
A conventional art has suggested a solid-state imaging device for reducing the capacitance of a detection capacitor (Japanese Laid-Open Patent Application No. H05-291550 Publication).
The signal accumulated in the detection capacitor 104 is normally read out as a voltage Vfd, and expressed byVfd=Qfd/Cfd 
where Qfd is the electric charge transferred from the photodiode 101 and accumulated in the detection capacitor 104, and Cfd is the capacitance of the detection capacitor 104. In order to obtain a more detailed signal as an image in a MOS-type solid-state imaging device in which pixels are arranged in an array, the cell size of a pixel needs to be reduced. As the cell size becomes smaller, the area of a photodiode becomes smaller and thus the amount of electric charge Qfd to be accumulated is reduced. Therefore, in the case where Qfd is a fixed value, Cfd needs to be reduced in order to increase Vfd.
In the conventional art, since Cfd is almost equal to Csub, Cfd can be reduced by reducing the area Sfd of the detection capacitor 104. Cfd is expressed as follows (see FIG. 4):Csub=ε·Sfd/dfd Cfd=Csub+Co+Cr+Cs+Cd 
where Csub is the capacitance between the detection capacitor 104 and the substrate 113, dfd is the distance between the detection capacitor 104 and the substrate 113, Cr is the capacitance between the detection capacitor 104 and the reset gate electrode 108, Co is the capacitance between the detection capacitor 104 and the transfer gate 103, Cs is the capacitance between the detection capacitor 104 and the amplifying transistor 105, and Cd is the capacitance between the source 115 and the drain 106.
However, with the increased miniaturization of the detection capacitor 104, it has become difficult to ignore not only Csub but also other capacitance elements relatively and thus to reduce Cfd. In order to reduce the capacitance Cfd, it is effective, for example, to reduce the capacitance Cr generated between the detection capacitor 104 and the adjacent transistor, namely, the reset transistor. Such reduction of capacitance makes it possible to improve the charge-to-voltage conversion efficiency in the detection capacitor 104.
In order to reduce the capacitance between the detection capacitor 104 and the reset transistor, the channel width W below the reset gate electrode 108 has to be decreased. It is simply expressed byCr=ε·Lr·W/(Lr/2)=2·ε·W 
where W is the channel width below the reset gate electrode 108, ε is the permittivity, and Lr is the gate length of the reset gate electrode 108. The channel width of a transistor is normally determined by the width of an active region. Since the width of an active region (channel width) is almost determined by the resolution of a stepper used for a lithography process in semiconductor manufacturing processes, it is difficult to decrease the width to less than 0.2 μm to 0.3 μm.